The following co-assigned U.S. Patent Applications and Patents are hereby incorporated by reference in their entireties: (1) U.S. patent application Ser. No. 09/704487, entitled xe2x80x9cWide Input Programmable Logic System And Methodxe2x80x9d, filed on Nov. 2, 2000; and (2) U.S. Pat. No. 6,067,252, entitled xe2x80x9cElectrically Erasable Non-Volatile Memory Cell With Virtually No Power Dissipationxe2x80x9d (Attorney Docket Number M-7435), filed on May 26, 1999.
The present invention relates generally to programmable devices. Specifically, the present invention relates to a programmable device and method with generic logic blocks.
Field-programmable gate arrays (FPGAs) and programmable logic devices (PLDs) have been used in data communication and telecommunication systems.
Conventional PLDs and FPGAs have a pre-determined number of non-configurable blocks, where each block performs a pre-determined function. Some currently-available CPLD products comprise arrays of logic cells. On high-density CPLD products, memory modules may be included. The memory module is usually limited to SRAM.
Conventional PLD devices and methods have several drawbacks, such as footprint requirements on a circuit board, limited speed and limited data processing capabilities.
One aspect of the invention relates to a programmable device. The device comprises a plurality of generic logic blocks. Each generic logic block comprises an array of product term circuits. Each product term circuit comprises a plurality of CMOS circuits. Each array of product term circuits is configurable to perform product term logic functions and a memory function.
Another aspect of the invention relates to a method of configuring a programmable device. The method comprises configuring a generic logic block in the programmable device to perform product term logic functions and a memory function, wherein each generic logic block has a substantially similar structure.
Another aspect of the invention relates to a logic block in a programmable device. The logic block comprises an array of product term circuits. Each product term circuit comprises a plurality of CMOS circuits. The array is configurable to perform product term logic functions and a memory function.
Another aspect of the invention relates to a macrocell in a configurable logic block in a programmable logic device. The generic logic block is configurable to perform logic functions and memory functions. The generic logic block comprises a plurality of product term circuits. Each product term circuit comprises a plurality of CMOS circuits. The macrocell comprises a register configured to store data output by a configurable set of the product term circuits.